The present invention relates to NAND flash memory devices and more particularly, to a NAND flash memory device having an enlarged interval between a selection transistor and the memory cell adjacent to the selection transistor.
A memory cell array of a NAND flash memory device is constructed in the unit of a string, including pluralities of cell strings therein. Each cell string includes selection transistors and pluralities of memory cells connected in series. The structure of the cell string is illustrated in FIG. 1.
FIG. 1 is a circuit diagram showing a conventional NAND flash memory device. A cell siring of the NAND flash memory device includes a drain selection transistor DST, a source selection transistor SST coupled to a common source line CSL, a plurality of word lines coupled to bitlines (BL0, BL1), and pluralities of memory cells MC0˜MC31 coupled between the drain and source selection transistors, DST and SST, in series.
In a general NAND flash memory device, the drain selection transistor DST, the source selection transistor SST, and the memory cells MC0˜MC31 have intervals (i.e., the distance between the transistors) that are about the same. Here, the memory cells may be arranged in 16, 32 or 64 memory cells in series in consideration with storage capacity and density of the device. The NAND flash memory device has pluralities of cell strings, each including 32 memory cells MC0˜MC31.
In the structure of the flash memory device, program disturbance occurs at the memory cell MC0, which is coupled to a deselected bitline BL0 and a wordline WL0 adjacent to a source selection line SSL, and at the memory cell MC31 that is coupled to a deselected bitline BL0 and a wordline WL31 adjacent to a drain selection line DSL. This phenomenon arises from the fact that during a programming mode, a ground voltage 0V, the power source voltage Vcc, and a pass voltage Vpass are applied to the source selection line SSL, the drain selection line DSL, and the rest except the wordline of the selected memory cell to be programmed, respectively, the channels of the source selection transistor SST, the drain selection transistor DST, and the memory cells are respectively charged with about 0V, 1V, and 8V.
In further detail, a strong electric field is generated between the source selection transistor SST and the memory cell MC0 by a voltage difference between a source voltage 0V of the source selection transistor SST and a channel voltage 8V of the memory cell MC0 adjacent to the source selection transistor SST. A strong electric field is also generated between the drain selection transistor DST and the memory cell MC31 by a voltage difference between the power source voltage Vcc of the drain selection transistor DST and a channel voltage 8V of the memory cell MC31 adjacent to the drain selection transistor DST.
As such, when there are lateral electric fields between the selection transistors SST and DST and the memory cells adjacent thereto, electrons, which are generated from the interfaces among the semiconductor substrate and the selection transistors SST and DST, move toward the memory cells along the surface of the semiconductor substrate and are referred to as hot electrons. These hot electrons move vertically and flow into a floating gate of the memory cell MC0 or MC31 not to be programmed, causing the memory cell MC0 or MC31 to be programmed undesirably.
As a voltage at the side of the source selection transistor SST is higher than that of the drain selection transistor DST, the electric field appears stronger at the side of the source selection transistor SST. Therefore, the program disturbance is more serious in the memory cell MC0 adjacent to the source selection transistor SST than the memory cell MC31 adjacent to the drain selection transistor DST.
FIG. 2 is a graphic diagram showing relations between threshold voltages (Vt) and pass voltages (Vpass) when program disturbance due to hot electrons occurs in the memory cells MC0 and MC31 shown in FIG. 1. It can be seen from FIG. 2, that the memory cells MC0 and MC31 coupled to the wordlines WL1 and WL31 are featured with characteristics quite different from the memory cells MC1 through MC30 coupled to the other wordlines WL1 through WL30. This is because of the program disturbance explained above.
Such program disturbance slows down a programming speed, degrading the performance of the device.